1. Field of the Invention
The present invention relates to integrated circuit fabrication, and, more particularly, to chemical mechanical polishing of semiconductor wafers.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas have been defined upon the substrate, a metal interconnect is placed on the semiconductor topography and connected to contact areas thereon. An interlevel dielectric is then deposited upon and between the metal interconnect, and more contact areas are formed through the dielectric to the interconnect routing. A second level of metal interconnect may then be placed upon the interlevel dielectric and coupled to the first level of metal interconnect via the contact areas arranged within the dielectric. Additional levels of metal interconnect and interlevel dielectric may be formed if desired.
Stacking metal interconnect levels relies on photolithography to align different levels of metal interconnect that make up an integrated circuit. In photolithography, alignment of the different features on the surface of the wafer is used to pattern the next level and create a working device. Due to the depth of focus limitations in photolithography, it is critical that the surface being patterned is as flat as possible. Unfortunately, unwanted surface irregularities may form in the topological surface of one or more layers of an integrated circuit. For example, a recess may result during the formation of conductive plugs which extend through an interlevel dielectric. Plug formation involves forming an opening through an interlevel dielectric and depositing a conductive material into that opening and across the interlevel dielectric. A recess may form in the upper surface of the conductive material since deposition occurs at the same rate upon the bottom of the opening as upon the sides of the opening. The formation of such recesses can lead to various problems during integrated circuit fabrication. For instance, step coverage may result from large thickness topography. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. In general, the height of the step, e.g., the depth of the recess, and the aspect ratio of the features being covered, e.g., the depth-to-width ratio of the recess, affects the step coverage. The greater the step height or the aspect ratio, the more difficult it is to achieve coverage of the step without a corresponding thinning of the film that overlies the step.
The concept of utilizing chemical and mechanical abrasion to remove surface irregularities and create a planar surface is known as chemical-mechanical polishing ("CMP"). A typical CMP process involves pressing a substrate, e.g., a semiconductor wafer device upside-down against a moving polishing pad which is adhesively attached to a rotatable steel table or steel platen. The steel platen provides rigidity and mechanical support to the polishing pad. A suspension of abrasive particles in a liquid often referred to as a "slurry," is deposited upon the pad possibly through a nozzle such that the slurry becomes disposed at the interface between the pad and the wafer surface. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The polishing process is facilitated by pressure between the pad and the wafer to remove material catalyzed by the slurry or mechanically remove materials from the pad without slurry catalysis. Thus, through both chemical and mechanical reactions, excess material is removed from the wafer.
The polishing pad may be made of various substances. Typically, it is desirable to use a polishing pad that is both resilient and, to a lesser extent, conformal. The selection of pad properties such as weight, density, and hardness often depends on the material being polished. A popular polishing pad comprises polyurethane. An example of a relatively hard polishing pad is the IC-1000.TM. type pad commercially available from Rodel Products Corporation of Newark, Del. A relatively soft pad is the SUBA 500.TM. type pad, also manufactured by Rodel Products Corporation. Polishing pads used for wafer planarization may undergo a reduction in polishing rate and uniformity due to loss of surface roughness. Furthermore, the pores of polishing pads may become embedded with slurry particles or polishing by-product. If the pores remain blocked over a substantial period of time, a condition known as "glazing" occurs. Glazing results when enough particles build up on the polishing pad surface such that the wafer surface begins to hydroplane over the surface of the pad. Hydroplaning eventually leads to substantially lower removal rates in the glazed areas, and, in some cases, to mechanical scratching.
A method known as pad conditioning is generally used to counter smoothing or glazing of the polishing pad surface and to achieve a stable polishing rate. Pad conditioning is herein defined as a technique used to maintain the polishing pad surface in a state which enables proper polishing of a topological surface. Pad conditioning is typically performed by mechanically abrading the pad surface in order to renew that surface. Such mechanical abrasion of the pad surface may roughen the surface and remove particles which are embedded in the pores of the polishing pad. Opening the pores permits the entrance of slurry into the pores during CMP to enhance polishing. Additionally, the open pores provide more surface area for polishing.
The current practice of utilizing slurries during CMP and pad conditioning causes corrosion effects on the steel platen. The slurry may comprise different chemicals including acidic materials, basic materials, and oxidizers. Generally when the acidic/oxidized components of a slurry remain in contact with the steel platen, e.g., the steel platen remains emerged in the slurry, the steel platen becomes susceptible to corrosion. Even though the polishing pad covers the steel platen, the steel platen corrodes over time due to localized cathodic and anodic sections being formed on the steel platen. Corrosion can contribute to several material defects in the steel platen leading to weakened structure and cracks. Ultimately, the corrosion may completely reduce the usefulness of the steel platen, in which case the steel platen must be replaced with a new steel platen. Steel platens are generally expensive, and thus each replacement of a steel platen increases the dollar cost. Furthermore, the replacement of a steel platen causes system downtime wherein production must be stopped, thereby further increasing dollar cost. Also, the corrosion may leak to the actual semiconductor wafer, thereby ruining the wafer completely.